View AK8816VG_7717395.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asahi kasei [ak8815/16] ms0331-e-00 1 2004 / 08 ak8815/16 ntsc/pal digital video encoder general description the ak8815/16 is a digital video encoder which is developed for portable apparatus applications such as cellular phone etc.. itu-r bt.601 level compatible y, cb,and cr signals which correspond to square pixel are encoded into either ntsc or pal compatible composite video signal. interface is made in hsync-, vsync- synchronized slave-mode operation. it is controlled via a 4-wire serial interface. features ? ntsc-m, pal-b, d, g, h, i encoding ? composite video output ? y:cb:cr 4:2:2 square pixel data input ? h/v slave operation ? y filtering: 2 x over-sampling ? c filtering: 4 x over-sampling ? 9-bit dac ? macrovision copy protection rev. 7.1 * (only ak8815 ) ? vbid ( cgms-a ) compatible ? wss compatible ? on-chip quartz crystal oscillator circuit ? clock: square pixel data rate 24.5454 mhz ( ntsc ), 29.50 mhz ( pal ) ? device control i / f : 4- wire serial bus interface ? on-chip color bar output ? black burst output ? internal operating voltage: 2.7 v ~ 3.3 v ? supplying interface power supply ( 1.6 v ~ 2.0 v or 2.7 v ~ 3.3 v ) ? power-down function ? monolithic cmos ? 57 pin fbga ( 5 mm sq ) ( lead-free package ) (*note) this device is protected by u.s. pat ent numbers 4,631,603, 4,577, 216, and 4,819,098, and other intellectual rights. the use of ma crovision?s copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay- per -view use only, unless otherwise authorized in written by macrovision. reverse engi neering or disassembly is prohibited.
asahi kasei [ak8815/16] ms0331-e-00 2 2004 / 08 block diagram vref generator avdd avss dvdd dvss vref iref xti/clkin input data control synchronization control subcarrier generator chroma lpf filter (x 2 interpolator) videoout sdo vsync hsync sclk cs sdi rstn pdn color bar & background color control cb/cr lpf filter (x 2 interpolator) y lpf filter (x 2 interpolator) sync generato r 9-bit dac d[7:0 ] clkout xto u-p i/f register timing controller cb cr y v u c clk generato r clkinv sin cos pvdd1 pvss1 pvdd2 pvss2 clkmd vbid & wss macrovision ud[4:0] test lo g ic test atpg xvdd
asahi kasei [ak8815/16] ms0331-e-00 3 2004 / 08 ordering guide ak8815/16vg 57 pin fbga pin layout 57pin fbga a b c d e f g h j 9 8 7 65432 1 bottom view
asahi kasei [ak8815/16] ms0331-e-00 4 2004 / 08 pin functional description (preliminary) no. pin name i/o function a7 xti/clkin i quartz crystal resonator connection pin ( to be grounded via a 18 pf capacitor as shown in the recommended circuit ). ntsc: 24.5454 mhz / pal: 29.50 mhz hi-z input is acceptable to this pin at pdn = l. input from an external crystal oscilla tor should be connected to this pin. b6 xto o quartz crystal resonator connection pin ( to be grounded via a 22 pf capacitor as shown in the recommended circuit ). ntsc: 25.5454 mhz / pal: 29.50 mhz dvss level is output on this pin at pdn = l. b5 clkmd i clock mode setting pin. should be connec ted to either dvdd or dgnd. gnd connection: when a crys tal resonator is used xvdd connection: when an external crystal oscillator is used b9 clkout o clock output pin. ntsc: 24.5454 mhz / pal: 29.50 mhz this becomes hi-z output at pdn =l. b7 clkinv i ?l ? : data is latched with rising edge. ?h? : data is latched with falling edge. internal clock is inverted (internal operat ion timing edge is inverted. clkout is not affected). connect to either dvdd or dgnd. j6 pdn i power down pin. after returning from pd mode to normal operation, reset sequence should be done to ak8815/16. ?l ?(gnd level): power-down ?h ?: normal operation j5 rstn i reset input pin. in order to initialize t he device , an initialization must be made in accordance with the reset sequence. ?l ? : reset ?h ? : reset hi-z input is acceptable to this pin at pdn = l. j4 sclk i serial data clock input pin. 15 mhz ( max ) hi-z input is acceptable to this pin at pdn = l. h4 sdi i serial data input pin. hi-z input is acceptable to this pin at pdn = l. h3 sdo o serial data output pin. this becomes high output at pdn = l. this pin interfaces one-to-one with a controller through a dedicated pin. h5 cs i serial data chip enable signal input pin. this pin interfaces one-to-one with a controller through a dedicated pin. l : disabled condition ( un-selected ) h : enabled condition ( selected ) hi-z input is acceptable to this pin at pdn = l. h8 d7 i data video signal input pin (msb). hi-z input is acceptable to this pin at pdn = l. g8 d6 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. h9 d5 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. g9 d4 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. f8 d3 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. e8 d2 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. d8 d1 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. d9 d0 i data video signal input pin (lsb). hi-z input is acceptable to this pin at pdn = l. j7 hsync i horizontal sync signal input pin. hi-z input is acceptable to this pin at pdn = l. h7 vsync i vertical sync signal input pin. hi-z input is acceptable to this pin at pdn = l. b3 vref o on-chip vref output pin. avss level is output on this pin at pdn = l. connect this pin to analog ground via a 0.1 uf or larger capacitor.
asahi kasei [ak8815/16] ms0331-e-00 5 2004 / 08 a2 iref o iref output pin. connect this pin to analog ground via a 12 kohm resistor ( better than +/_ 1% accuracy ). c1 videoout o video output pin. connect this pin to analog ground via a 390 ohm resistor resistor ( better than +/_ 1% accuracy ). c2 avdd p analog power supply pin. a5 xvdd p power supply pin for crystal ( for xtal ). b2 avdd p analog power supply pin. b1 avss g analog ground pin. d1 dvss g digital ground pin. a6 dvss g crystal ground connection pin ( set dvss [0 v] ). a3 avss g analog ground pin. f1 dvdd p digital power supply ( digital core power supply ) f9 dvdd p digital power supply ( digital core power supply ) e2 dvss g digital ground pin ( digital core ground ) e9 dvss g digital ground pin ( digital core ground ) c8 pvdd1 p power supply pin for chip pad. i / f power supply for clkout, d[7:0], hsync, vsync c9 pvss1 g ground pin for pvdd1 j3 pvdd2 p power supply pin for chip pad. i / f power supply for pdn, rstn, sdo, sdi, cs, sclk. h2 pvss2 g ground pin for pvdd2 a4 avss g ground pin for the substrate biasing connect to analog ground. b8 test i for normal operation, connect to ground. a8 atpg i for normal operation, connect to ground. h1 dvdd p digital power supply j2 ud4 o test output pin. for norma l operation, left un-connected ( nc ). g1 ud3 o test output pin. for norma l operation, left un-connected ( nc ). g2 ud2 o test output pin. for norma l operation, left un-connected ( nc ). e1 ud1 i/o test i/o pin. for normal operation, left un-connected ( nc ). d2 ud0 i/o test i/o pin. for normal operation, left un-connected ( nc ). a1 nc - nc pin. a9 nc - nc pin. j1 nc - nc pin. j9 nc - nc pin. b4 nc - nc pin h6 nc - nc pin. j8 nc - nc pin. f2 nc - nc pin. c3 n.c. - index pin
asahi kasei [ak8815/16] ms0331-e-00 6 2004 / 08 electrical characteristics (1)absolute maximum ratings parameter min max units supply voltage (vdd) (note1) dvdd, xvdd,avdd, pvdd1, pvdd2 -0.3 4.6 v input pin voltage (vin) -0.3 vdd+0.3 v input pin current (iin) (note2) - +/- 10 ma storage temperature -40 +125 c ( note1) when each ground pin ( dvss, avss, pvss1, pvss2 ) is at 0 v ( voltage reference ). in this specification, pvdd1 and pvdd2 are expr essed as pvdd ( as a general comment ) hereafter. similarly, dvdd, xvdd are express ed as dvcc, and avdd and avdd as avdd. each ground pin is always kept to the same re ference voltage, 0 v with no potential difference. (note2) exclude power supply pin. (2) recommended operating conditions parameter min typ. max units power supply (dvdd = avdd ) (note1 ) 2.7 3.0 3.3 v interface power supply (note2) (pvdd = dvcc ) at 3.0 v i/f 2.7 .3.0 3.3 v interface power supply (pvdd1, 2 ) at 1.8 v i/f 1.6 1.8 2.0 v operating temperat ure (ta) -20 25 85 c note 1) excluding interface power supply. 1.8 v power supply can be supplied only to the interface part. note 2) interface power supplies pvdd1, pvdd2 c an be used as 3 v or 1.8 v power supply interface each. but when the 1.8 v interface is not selected, same potential as dvcc is used as interface power supply. (example pvdd1 = 1.8 v, pvdd2 = dvdd = 3 v) note 3) as described at the note in item ( 1 ) abov e, pvdd1 and pvdd2 are expressed as pvdd in this table. similarly, dvdd and xvdd are expr essed as dvcc, and avdd and avdd as avdd. (3) dc characteristics [operating voltages : dvdd 2.7 v ~ 3. 3v / pvdd 2.7 v ~ 3.3 v / pvdd 1.6 v ~ 2.0 v, temperature : -20 ~ 85 c] parameter symbol min typ max units conditions vih1 0.7pvdd pvdd = 3.0v digital input h voltage vih2 0.8pvdd v pvdd = 1.8v vil1 0.3pvdd pvdd = 3.0v digital input l voltage vil2 0.2pvdd v pvdd = 1.8v digital input leakage current il +/- 10 ua voh1 2.2 v ioh= 1ma i/o 3.0v digital output h voltage ( excluding xto ) voh2 1.3 ioh= 600ua i/o 1.8v vol1 0.4 v iol= 2m a i/o 3.0v digital output l voltage ( excluding xto ) vol2 0.4 v iol= 1m a i/o 1.8v
asahi kasei [ak8815/16] ms0331-e-00 7 2004 / 08 (4) analog characteristics [ operating voltage : avdd = dvcc= 2.7 - 3.3 v, temperature : -20 - 85 c ] parameter min typ max units conditions resolution 9 bit integral non-linearity ( error ) +/- 0.6 +/- 2.0 lsb differential non-linearity ( error ) +/- 0.4 +/- 1.0 lsb output full scale voltage 1.21 1.28 1.35 v note1) output offset voltage 5.0 mv note2) on-chip reference voltage 1.17 1.23 1.30 v reference voltage drift -50 ppm/ c note1) values are when a 390 ohm output load, a 12 kohm iref pin resistor and on-chip vref are used. full scale output current is calculated as iout = full sca le output voltage ( typ. 1.28 v ) / 390 ohm = typ. 3.28 ma. note2) a voltage referenced to vss when a dec imal zero voltage is input to dac. (5) power consumption [ operating voltage : avdd = dvcc= 2.7 - 3.3 v, temperature : -20 - 85 c ] parameter min typ max units conditions total power consumption 24 36 ma note3) power-down current 1 10 100 ua note4) power-down current 2 1 10 ua note5) xtal part current 2.0 3.3 ma note6) analog part operating current 1 6.5 ma note7) analog part operating current 2 1.6 a note8) note3) ntsc mode on-chip color bar output is enabl ed and dac is ? on ? ( no external output loads are connected , other than those re commended, connecting-components ). note4) measuring conditions : input / output settings after power-down sequence are, pdn pin is at gnd level, clkout and sdo output are at high level ( power supply voltage ) with no external connection, input voltage on those input pins is 1/2 level of power supply which are set to accept hi-z i nput at power-down, and test = atpg = gnd ( or left open ). power supplies are avdd = dvcc = pvdd. each ground pin ( dvss, avss1, avss2, pvss1, pvss2 ) is always 0 v ( voltage reference ). note5) measuring conditions : set avdd = dvcc = 0 v ( potential difference with voltage reference ground is 0 v ) in power-down current 1 condition.set those input pins to gnd level which are set to accept hi-z input at power-down. power-down current 2 is pvdd power supply current at pvdd = 1.6 v ~ 1.8 v or 2.7 v ~ 3.3 v. note6) at rstn = h, pdn = h note7) when dac output is ? on ?. note8) when dac output is ? off ? .
asahi kasei [ak8815/16] ms0331-e-00 8 2004 / 08 (6) crystal oscillator circuit part crystal resonator and externa lly connecting load capacitance parameter symbol min typ max units conditions oscillating frequency f0 24.5454 29.5000 [mhz] frequency accuracy ? f/f +/-50 [ppm] load capacitance cl 15 [pf] effective equivalent resistance re 100 [ ? ] note1) parallel capacitance c0 0.85 [pf] externally connecting load capacitance on xtli pin cxi 18 [pf] externally connecting load capacitance on xtlo pin cxo 22 [pf] note 1 ) effective equivalent resistance is generally given as re = r1 x ( 1 + co / cl ) square where r1 : equivalent series resistance of crystal resonator co : parallel capacitance of crystal resonator circuit connection example gm cxi =18pf cxo =22pf rf xtli xtlo ak8815 rd rd: please refer the x?tal specification
asahi kasei [ak8815/16] ms0331-e-00 9 2004 / 08 ac timing ( pvdd = 2.7 v ~ 3.3 v / pvdd = 1.6 v ~ 2.0 v, temperature : ?20 ~ 85 c) loading condition : cl = 30 pf ( at 3.0 v i/f ) cl = 15 pf ( at 1.8 v i/f ) (1) clk ( 1-1 ) clkmd = dvss : when a crystal resonator is connected ( +/_ 50 ppm ) clkout fclk tclkh tclkl vih1, vih2 1/2 pvdd1 vil1, vil2 parameter symbol min. typ. max unit conditions 24.5454 ntsc clkout fclko 29.500 mhz pal tclkil, tclkih : minimum pulse width 10 ns guaranteed by design external input clock ac timing ( dvcc = 2.7 v ~ 3.3 v : -20 ~ 85 c ) ( 1-2 ) clkmmd = xvdd : when an external clock source is input ( +/_ 50 ppm ) clkin fclki tclkih tclkil vil1 vih1 1/2 dvcc parameter symbol min. typ. max unit conditions 24.5454 ntsc clkin fclki 29.50 mhz pal clkin duty pclkid 40 60 % tclkil, tclkih : minimum pulse width 12 ns ( tr / tf = < 2 ns at 10 % - 90 % level of power supply )
asahi kasei [ak8815/16] ms0331-e-00 10 2004 / 08 (2) pixel data input timing tds tdh d7:d0 hsync vsync clkout vih1, vih2 vil1, vil2 vih1, vih2 vil1, vil2 clkinv = low, -20 ~ 85 c ( loading condition : cl = 30 pf at 3 v i/f / 15 pf at 1.8 v i/f ) parameter symbol min. typ. max unit conditions data setup time tds 8 nsec data hold time tdh 5 nsec above values are specified at t he ak8815/16 device pin terminal and do not include interconnection delays of pc board etc.. when clkinv = high, similar tds and tdh ar e specified at the falling edge of clkout. (3) hsync pulse width hsycn p hsw parameter symbol min. typ. max unit conditions 15 115/16 ntsc (24.5454mhz) hsync pulse width phsw 15 139 clks pal (29.50mhz) * typical values are calculated by converting the h sync pulse width of analog video specification into number of system clock pulses.
asahi kasei [ak8815/16] ms0331-e-00 11 2004 / 08 (4) reset (4-1) reset timing rstn pres clkout 1 2 99 100 parameter symbol min. typ. max unit rstn pulse width pres 100 sysclk (4-2) power down sequence / reset sequence before pdn setting ( pdn to low ), reset must be enabled for a duration of longer-than-100 clock time. after pdn release ( pdn to high ), reset must be enabled for 10 ms or longer till analog part reference voltage & current are stabilized. vil1, vil2 vih1, vih2 rstn pdn clkin clkout hres sres vih1, vih2 hi-z ok low sclk, scs tscll (clkout=h) sdo (sdo=h) gnd parameter symbol min. typ. max unit rstn pulse width sres 100 sysclk time from pdn to high to rstn to high hres 10 msec scl low duration before rstn to rise tscll 50 nsec at power-down, all control signals must surely be set to either power supply or ground level of the selected power supply, and not to vih / vil levels.
asahi kasei [ak8815/16] ms0331-e-00 12 2004 / 08 ( 5 ) serial i / f timing waveform ( 5-1 ) write / read data input timing tsckh cs a7 vih1, vih2 a6 a5 a4 tcss scl k sdi tsds tsdh tsckl sdo high 1/2 level of vih1 ( 2 ) /vil1 ( 2 ) tclk vih1, vih2 vil1, vil2 ( 5-2 ) write data input timing cs d3 vih1, vih2 d2 d1 d0 tcsw scl k sdi sdo tcsl vil1, vil2 high vil1, vil2
asahi kasei [ak8815/16] ms0331-e-00 13 2004 / 08 ( 5-3 ) read data output timing cs a1 a0 d7 d6 sclk sdi sdo d5 tsdco vih1, vih2 vil1, vil2 vih1, vih2 vil1, vil2 ( 5-4 ) read data output timing 2 cs vil1, vil2 tcsw scl k sdo d3 d2 d1 d0 sdi tcsl tsdz vih1, vih2 parameter symbol min typ max unit time from cs to high to sclk to high tcss 20 nsec sclk frequency tclk 15 mhz sclk ?high? duration tsckh 26 nsec sclk ?low? duration tsckl 26 nsec data set-up time tsds 15 nsec data hold time tsdh 10 nsec time from 15/16 th sclk to low to cs to low tcsl 20 nsec cs ?low? duration tcsw 60 nsec sdo output delay time tsdco 20 nsec sdo output hold time tsdh 0 nsec when to execute sequential write/read to/from register, cs must be kept to low once
asahi kasei [ak8815/16] ms0331-e-00 14 2004 / 08 functional outline ( 1 ) reset ( 1-1 ) reset of serial interface part ( asynchronous reset ) reset is made by setting rstn pin to low. ( 1-2 ) reset of other than serial interface blocks reset is made by keeping rstn pin low for a longer than 100 clock time, in normal operation. ( 1-3 ) at power-on-reset ( including power-down release case ) follow the power-on-reset sequence. at the completion of each initialization, all internal regist ers are set to default values ( refer to register map ). right after the reset, video output of t he ak8815/16 is put into hi-z condition. ( 2 ) power-down it is possible to put the device into power-down m ode by setting the ak8815/16 power-down pin to gnd. transition to power-down mode should be followed by the power-down sequence. as for the recover from the power-down mode, it should be followed by the power-down release sequence. ( 3 ) master clock as a master clock of the ak8815/16, either a crystal resonat or or a crystal oscillator c an be used. either of the operation mode ( a crystal resonator or a crys tal oscillator ) is selected by clkmd pin. crystal resonator mode : clkmd dvss crystal oscillator mode : clkmd xvdd when a crystal resonator is used, connect a resonator between xti pin and xto pin. an oscillating frequency to be used differs in nt sc encoding operation and in pal encoding operation. a clock frequency to be used is as follows : in ntsc encoding operation : 24.5454 mhz in pal encoding operation : 29.50 mhz when a crystal oscillator is us ed, connect it to xti pin. when clkinv = l, same rising clock as clkout ri se is used as an internal encoder clock, but when clkinv = h, internal encoder is operated by using an inverted clock. even when clkinv is altered, clo ck phase of clkout is not changed. ( 4 ) video signal interface video input signal ( data ) is processed in slave operat ion mode which is synchronized with hsync / vsync. when clkinv = dvss, external input is latched at the rising edge of clock ( 5 ) pixel data input data to the ak8815/16 is ycbcr ( 4:2:2 ). data with y : 15/16 ~ 235 and cbcr : 15/16 ~ 240 should be input. ( 6 ) video signal conversion video re-composition module converts t he multiplexed data ( itu-r bt.601 level y, cb, cr ) into interlaced ntsc-m and pal-b, d, g, h, i data. video enc oding setting is done by ? mode register ?.
asahi kasei [ak8815/16] ms0331-e-00 15 2004 / 08 ( 7 ) luminance signal filter ( luma filter ) luminance signal is output via lpf ( see x2 luma filter in the block diagram ). -50 -40 -30 -20 -10 0 10 0 . 0 1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0 1 0 . 0 1 1 . 0 1 2 . 0 1 3 . 0 frequency[mhz] gain[db] ( 8 ) chroma signal filter ( chroma filter ) chroma input signal components ( cb, cr ) prior to t he modulation go through a 1.3 mhz band limiting filter ( see 4:2:2 to 4:4:4 x2 interpolator in the block diagram ). chroma signal which is modulated by the sub-carrier is out put via a low pass filter ( chroma lpf in the block diagram ). frequency response of each f ilter is shown below. 4:2:2 to 4:4:4 inte rpolator filter -50 -40 -30 -20 -10 0 10 0.00.51.01.52.02.53.03.54.04.55.05.56.06.5 frequency[mhz] gain[db] x 2 interpolator filter -50 -40 -30 -20 -10 0 10 0 . 0 1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0 1 0 . 0 1 1 . 0 1 2 . 0 1 3 . 0 frequency[mhz] gain[db]
asahi kasei [ak8815/16] ms0331-e-00 16 2004 / 08 ( 9 ) color burst signal burst signal is generated by a 32 bi t digital frequency synthesizer. color burst frequency is selected by mode setting of ntsc / pal. standerd subcarrier freq (mhz) video process 1 vmod-bit ntsc-m 3.57954545 0 pal-b,d,g,h,i 4.43361875 1 burst signal table ( 10 ) video dac the ak8815/16 has a 9 bit resolution, current-drive dac as a video dac which runs at 29.5 / 24.5454 mhz clock frequency. this dac is designed to output 1.28 v o-p at full scale under the following conditions ? loading resistance of 390 ohms, vref at 1. 23 v and iref pin resistor of 12 kohms. here iref pin resistor means a resistor connected between [ iref ] pin and ground. dac output voltage can be adjusted by adjusting iref pin resistor. [ vref ] pin should be connected to ground via a 0.1 uf or larger capacitor. dac output can be turned ?on? or ?off? by register setting and current consumption can be lowered. when the output is turned off, it is put into high impedance condition. on-chip vref circuit is kept active and only the dac output is turned off then.
asahi kasei [ak8815/16] ms0331-e-00 17 2004 / 08 ( 11 ) video data interface timing ( 1-1 ) video interface the ak8815/16 operates in slave mode which is sync hronized with the hsync / vsync sync signals. a system operational outline is as follows ? operation clock of the controller dev ice which feeds data to the video encoder is fed from the video encoder. and such timing signals as hsync and vsync of the cont roller are generated by the same clock timing. the ak8815/16 synchronizes its operation wi th the generated hsync and vsync signals. c ontroller video encoder clk hsync vsync data in normal operation, the ak8815/16 checks h sync and vsync changes at each clk edge ( clk synchronized ). a pixel when hsync is identified to get low is recognized to be h0 ( zero ), and the 236 th data ( ntsc ) or the 310 th data ( pal ) is taken as cb0 square pixel data. video field is recognized by vsync relation over hsync. field recognition is made as follows : the ak8815/16 distinguishes at every field if it is odd field ( 1 st field ) or not. even field sync signal is not usually input. 1 ) when vsync timing pulse signal fed to the ak8815/16 becom es low from high while hsync input signal is at low, this field is interpreted as odd field. the horizontal line where odd field identification is m ade, functions as line 4 in ntsc mode and line 1 in pal mode ( even when both vsync and hsync are identified to get low simultaneously, it is processed as odd field. but it is recommended to input those si gnals with more than a few clock margin ). 2 ) the ak8815/16 continues operation in self-running mode , based on the sync signals whic h are fed just before, if horizontal / vertical sync signals are not fed every time in such timing and pulse count as expected in the video standard specifications. but it is recommended to input those sync signals in t he specified timing every time in order to prevent erroneous operation. 3 ) all other vsync than those identified to be odd field are processed as even field. but a use of vsync pulse other than in odd field synchronization is not assumed for normal operation.
asahi kasei [ak8815/16] ms0331-e-00 18 2004 / 08 ( 1- 2 ) pixel data in each line ( 1 ) ntsc clkout (24.5454mhz) d[7:0] cb0 y0 cr0 y1 cb1 cr319 y639 hsync 640 2 clock active video area (0x80) (0x10) (0x80) (0x10) (0x80) (0x10) (0x10) h0 1559 0tbd 236 237 238 239 240 1516 1515 1514 * ) when d [7:0], hsync and clkout are in same phas e relation as a timing example above, the ak8815/16 takes input data at the falling edge of each clkout if clkinv = h. * ) as an input data other than during active video period, black level ( c / y = 0x80 / 0x10 ) or other than 0x00 / 0xff codes in non hi-z state should be input. (2) pal clkout (29.5mhz) d[7:0] cb0 y0 cr0 y1 cb1 cr383 y767 hsync 768 2 clock active video area (0x80) (0x10) (0x80) (0x10) (0x80) (0x10) (0x10 ? h0 1887 0 tbd 310 311 312 313 314 1844 1845 1846 * ) when d [7:0], hsync and clkout are in same phas e relation as a timing example above, the ak8815/16 takes input data at the falling edge of each clkout if inv = h. * ) as an input data other than during active video period, black level ( c / y = 0x80 / 0x10 ) or other than 0x00 / 0xff codes in non hi-z state should be input.
asahi kasei [ak8815/16] ms0331-e-00 19 2004 / 08 ( 1-3 ) hsync and vsync relation in each frame ( 1 ) ntsc ( frame ) 525 line 480 active lines the first field ( odd ) hsync vsync 4 5 6 7 22 23 3 1 525 2 261 262 263 264 240 lines 263 lines * ) vsync negative-going occurs dur ing hsync = l at line 4. vsync positive-going can occurs at arbitrary location, but keep vsync low for 3 line duration time as a rough idea. the second field ( even ) hsync vsync 267 268 269 270 285 286 266 264 263 265 524 525 1 2 240 lines high 262 lines * ) vsync negative-going is not required for the second field. it is required for the first field only. when vsync is input in the specified timing (described below ) at the second field, the line and the field are set once as the second field. but since the burst cycle etc. is referenc ed to the first field, vsync synchronization cannot be made with the second field only. system synchronizati on must be made to reference the vsync synchronization at the fi rst field. when to input vsync at the second field, it should be done after the first 1/2 h of the 266 th line and before the falling edge of the 267 th hsync ( if hsync falling edge timing of the 266 th line is counted as the 0 th clock, vsync should be fallen after the 780 th clock and before the 1559 th clock ).
asahi kasei [ak8815/16] ms0331-e-00 20 2004 / 08 ( 2 ) pal ( frame ) 625 line 576 active lines the first field ( odd ) hsync vsync 4 5 22 23 24 3 1 625 2 310 311 312 313 288 lines 313 lines 314 * ) vsync negative-going occurs dur ing hsync = l at line 1. vsync positive-going can occur at arbitrary location, but as a rough idea, keep vsync low for 2.5, or 2 or 3 line duration time . the second field ( even ) hsync vsync 317 318 335 336 337 316 314 313 315 623 624 625 1 288 lines 313 lines 2 high * ) vsync negative-going is not requir ed for the second field. it is required for the first field only. when vsync is input in the specified timing (described below) at the second field, the line and the field are set once as the second field. but since the burst cycle etc. is referenced to the first fi eld, vsync synchronization cannot be made at the second field only. system synchronization must be made to referenc e the vsync synchronization at the first field. when to input vsync at the second field, it should be done after the first 1/2 h of the 313 th line and before the falling edge of the 314 th hsync ( if hsync falling edge timing of the 313 th line is counted as the 0 th clock, vsync should be fallen after the 944 th clock and before the 1887 th clock ).
asahi kasei [ak8815/16] ms0331-e-00 21 2004 / 08 ( 2-1 ) sync signal waveform, burst waveform generator ( 2-1-1 ) ntsc-j 90% 50% 10% 50% sync rise time sync horizontal reference point 50% sync level 50% h . ref. to b urst start burst height burst measurement point value consumer quality tolerance units total line period(derived) 63.556 usec sync level 40 +/- 3 ire sync rise time 10% - 90% 140 max 250 nsec horizontal sync width 50% 4.7 +/- 0.1 usec horizontal reference point to burst start 50% 19 defined by sc/h cycles burst * 50% 9 +/- 1 cycles burst height ** 40 +/- 3 ire * there is a case where tolerance of sync rise time is added to sync width tolerance. * measurement of burst time length is made between the burst start point which is defined as the zero-cross point, preceding the first half-cycle of the sub-carrier where burst amplitude becomes higher than 50 % level and the burst end point , defined in the same manner. 9 cycles +/- 1cycle 19 cycles +/-40 50% ntsc signal
asahi kasei [ak8815/16] ms0331-e-00 22 2004 / 08 ( 2-1-2 ) vertical sync signal timing ( ntsc ) 3h 3h 1 2 3 4 5 6 7 89 0.5h 3h 3h 3h 263 264 0.5h 3h 265 266 267 268 269 270 271 272 273 21 285 equalizing pulse and serration pulse equalizing pulse serration pulse g h 40ire i i i i +/-3ire symbol measurement point value recommended tolerance units g pre-equalizing pulse width 50% 2.3 +/- 0.1 usec h vertical serration pulse width 50% 4.7 +/- 0.2 usec g post-equalizing pulse width 50% 2.3 +/- 0.1 usec i sync rise time 140 max 250 nsec * there is a case where tolerance of sync rise time is added to pulse width tolerance.
asahi kasei [ak8815/16] ms0331-e-00 23 2004 / 08 ( 2-1-3 ) pal-b, d, g, h, i 90% 50% 10% 50% sync rise time horizontal sync horizontal reference point 50% sync level 50% h . ref. to b urst start burst height burst measurement point value consumer quality tolerance units total line period(derived) 64.0 usec sync level 300 +/- 20 mv sync rise time 10% - 90% 0.2 max 0.3 usec horizontal sync width 50% 4.7 +/- 0.2 usec horizontal reference point to burst start 50% 5.6 +/- 0.1 usec burst * 50% 10 +/- 1 cycles burst height ** 300 +/- 30 mv * there is case where tolerance of sync ri se time is added to sync width tolerance.
asahi kasei [ak8815/16] ms0331-e-00 24 2004 / 08 ( 2-1-4 ) vertical sync signal timing and burst phase pal-b, d, g, h, i pal-b,d,g,h,i 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b a b 623 624 625 123 4 56 8 7 622 621 620 a b 623 624 625 123 4 56 8 7 622 621 620 a : phase of burst : nominal value + 135 b : phase of burst : nominal value - 135 since burst frequency and line frequency are not practically in integer-multiple relation, specified phase value is not exactly 135 degrees. diagram below shows phase direction. equalizing pulse and serration pulse equalizing pulse serration pulse g h 300mv i i i i +/-30mv symbol measurement point value recommended tolerance units g pre-equalizing pulse width 50% 2.35 +/- 0.1 usec h vertical serration pulse width 50% 4.7 +/- 0.2 usec g post-equalizing pulse width 50% 2.35 +/- 0.1 usec i sync rise time 200 max 300 nsec * there is a case where tolerance of sync rise time is added to pulse width tolerance.
asahi kasei [ak8815/16] ms0331-e-00 25 2004 / 08 ( 12 ) on-chip color bar the ak8815/16 can output color bar signal. color bar signal to be generated has 100 % amplitude and 100 % saturation levels. color bar signal is output by setting register. when to output color bar signal, there are 2 modes of oper ation ? one is external sync timing mode for normal operation, and the other is in ternal self-operation mode. in internal self-operating mode, required timing is inte rnally generated automatically. namely, it is no need to input synchronization timing from outside of the chip. operation mode setting is done by mode register. when bbg-bit is set, bbg-bit is prio ritized ( black burst is output ). blanking level 100%white synctip level white yellow cyan green magenta red blue black the following values are code for itu-r. bt601 white yellow cyan green magent a red blue black cb 128 15/16 15/166 54 202 90 240 128 y 235 210 170 145 106 81 41 15/16 cr 128 146 15/16 34 222 240 110 128 ( 13 ) black burst signal generation function the ak8815/16 can output black burst signal ( black level output ). when to output black burst signal, there are 2 modes of operation ? one is external sync timing mode for normal operation , and the other is internal self-operation mode. in internal self-operation mode, required timing is inte rnally generated automatically. namely, it is no need to input synchronization timing from outside of the chip. when bbg-bit of [ mode register ] is set to ?1?, same oper ation is processed as in the case where fixed-15/16 y signal and fixed-128 pb / pr signal outputs are input. operation mode setting is done by mode register setting.
asahi kasei [ak8815/16] ms0331-e-00 26 2004 / 08 (14) video id the ak8815/16 supports to encode the video id ( eiaj cp r-1204 ) which distinguishes the aspect ratio etc.. this is also used as cgms ( c opy generation management system ). turning ?on/off? of this function is made by setting both vmod-bit = 0 and vbid-bit = 1 of { mode register (0x00) }. and data to be set is written into { vbid / wss data1 & 2 registers ( 0x01,0x02 )}. video id information is the highest order of priority information among vbi information ( when simultaneous outputs occur with macrovision signaling, only the vbi information is super-imposed on this line ). vbid data update timing . vsync new data data old data new data u-p data set control register vbid code assignment 20 bit data is configured with word0 = 2 bit, word1 = 4 bit, word2 = 8 bit and crc = 6 bit. crc is automatically calcul ated and added by the ak8815/16. default values of crc polynomial expression x6 + x + 1 are all ones. -data configuration bit1 bit20 data word0 2bit word1 4bit word2 8bit crc 6bit vbid waveform ref. bit1 bit2 bit3 bit20 ??? 2.235usec +/- 50nsec 11.2usec +/- 0.3usec 49.1usec +/- 0.44usec 1h 70ire +/- 10ire 0ire + 10 ire ? 5 ire 525/60 system amplitude 70ire encode line 20/283
asahi kasei [ak8815/16] ms0331-e-00 27 2004 / 08 ( 15 ) wss function the ak8815/16 supports to encode the wss ( itu-r. bt .1119 ) which distinguishes the aspect ratio and sets cgms-a etc.. turning ?on/off? of this function is made by setting both vmod-bit = 1 and wss-bit = 1 of { mode register ( 0x00 ) }. and data to be set is written into { vbid / wss data1 & 2 registers ( 0x01, 0x02 )}. wss data update timing vsync new data data old data new data u-p data set control register wss waveform 10.5usec 27.4usec 38.4usec 500mv +/- 5% 11.0 +/- 0.25usec 44.5usec 1.5usec 0 h encode line : former half of line 23 ( blank output during latter half ) coding : bi-phase modulation coding clock : 5 mhz ( ts = 200 ns ) encoding details as follows run-in start code group 1 aspect ratio group 2 enhanced services group 3 subtitles group4 reserved 29 elements 24 elements 24 elements 24 elements 18 elements 18 elements bit numbering 0 1 2 3 lsb msb 0 : 000111 1 : 111000 bit numbering 4 5 6 7 lsb msb 0 : 000111 1 : 111000 bit numbering 8 9 10 lsb msb 0 : 000111 1 : 111000 bit numbering 11 12 13 lsb msb 0 : 000111 1 : 111000 0x1f1c71c7 0x1e3c1f
asahi kasei [ak8815/16] ms0331-e-00 28 2004 / 08 power up sequence power-up sequence ( power supply turn-on sequence ) a vdd dvdd rstn raise rstn high after crystal resonator oscillation is stabilized ~ 5 ms xti vref raise rstn high after vref is stabilized >= 10 ms (min.) power on pdn hi-z ok low scl pvdd1 pvdd2 power-down release sequence a vdd/dvdd pvdd1/pvdd2 pdn rstn raise rstn high after crystal resonator oscillation is stabilized ~ 5 ms xti vref raise rstn high after vref is stabilized >= 10 ms (min.) pdn off hi-z ok low scl
asahi kasei [ak8815/16] ms0331-e-00 29 2004 / 08 device control sequence device control interface following modes of operations are contro lled via 4-wire serial interface. hi-z inputs to cs, sclk, and sdi pins are inhibi ted, except at power- down ( pdn pin = low ). write sequence: a5=0 cs scl k a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sdi 0 read sequence: a5=1 cs scl k a7 a6 a5 a4 a3 a2 a1 a0 sdi d7 d6 d5 d4 d3 d2 d1 d0 sdo high high 1 a5 bit becomes an identification tab a5 1 : read a5 0 : write cs must be set to low at every address change.
asahi kasei [ak8815/16] ms0331-e-00 30 2004 / 08 register map address register default r/w function 0x00 mode register 0x00 r/w mode set register 0x01 vbid/wss data 1 register 0x00 r/ w vbid data is set, wss data is set 0x02 vbid/wss data 2 register 0x00 r/ w vbid data is set, wss data is set 0x03 device id and revision id register 0x06 r register for device id and revision id 0x04 reserved 0x00 r/w 0x05 input control register 0x00 r/w input control register fo r out-of-standard quality input signal 0x06 reserved 0x0f r/w 0x07 reserved 0xfc r/w 0x08 reserved 0x20 r/w 0x09 reserved 0xd0 r/w 0x0a reserved 0x6f r/w 0x0b reserved 0x0f r/w 0x0c reserved 0x00 r/w 0x0d reserved 0x00 r/w 0x0e reserved 0x0c r/w 0x10 reserved 0xe3 r/w 0x11 reserved 0xf3 r/w 0x12 reserved 0x09 r/w 0x13 reserved 0xbd r/w 0x14 reserved 0x66 r/w 0x15 reserved 0xb5 r/w 0x15/16 reserved 0x90 r/w 0x17 reserved 0xb2 r/w 0x18 reserved 0x7d r/w
asahi kasei [ak8815/16] ms0331-e-00 31 2004 / 08 mode register (r/w) [address 0x00] sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac bbg cbg mas wss vbid scr vmod default value 0 0 0 0 0 0 0 0 sys1_reg definition bit register name r/w definition bit 0 vmod video mode bit r/w 0: ntsc 1: pal bit 1 scr sub-carrier reset bit r/w 0: sub-carrier reset off 1: sub-carrier reset bit 2 vbid vbid set register r/w 0: vbid off 1: vbid on bit 3 wss wss set register r/w 0: wss off 1: wss on bit 4 masmd master mode bit r/w master mode bit to set sync mode when color bar signal and black burst signal are generated 0 : operation by an external sync timing 1 : operation by an internal self -operating mode ( master mode ) bit 5 cbg color bar generator bit r/w 0: off 1: on when bbg is set, bbg is prioritized. bit 6 bbg black burst generator bit r/w 0: off 1: on bit 7 dac dac set bit r/w 0: dac off 1: dac on
asahi kasei [ak8815/16] ms0331-e-00 32 2004 / 08 vbid/wss 1 register (r/w) [address 0x01] vbid/wss 2 register (r/w) [address 0x02] video id and wss data setting are made. a common data r egister is used for both video id and wss data. when vbid bit of mode register is set in ntsc m ode, data is for vbid data ,and when wss bit of mode register is set in pal mode, data is for wss data. when vbid-bit is ?1? and vmod-bit is ?0? in mode register, the following bits are assigned. sub address 0x01 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbid7 vbid8 vbid9 vbid10 vbid11 vbid12 vbid13 vbid14 default value 0 0 0 0 0 0 0 0 sub address 0x02 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbid1 vbid2 vbid3 vbid4 vbid5 vbid6 default value 0 0 0 0 0 0 0 0 note ) ?0? should be written into reserved bits. vbid1 ---- vbid14 above correspond to the bit 1 ---- bit 14 wh ich are described at { vbid data code assignment } in { ( 14 ) video id } section. a 6-bit crc code from bit 15 ~ bit 20 is automatically added by the ak8815/16. data is retained till data is updated to a new one. following bits are assigned when wss-bit is ?1? and vmod-bit is ?1? in mode register. sub address 0x01 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g2-7 g2-6 g2-5 g2-4 g1-3 g1-2 g1-1 g1-0 default value 0 0 0 0 0 0 0 0 sub address 0x02 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved g4-13 g412 g4-11 g3-10 g3-9 g3-8 default value 0 0 0 0 0 0 0 0 note ) wss data is written with 0x01 first, then 0x02 in this order. when the 2 nd byte ( 0x02 ) of wss data is wr itten, the ak8815/16 interprets t hat data is updated to a new one and then encodes it to the next video line ( line 23 ). data is retained till data is updated to a new one.
asahi kasei [ak8815/16] ms0331-e-00 33 2004 / 08 device id and revision id register (r) [address 0x03] sub address 0x03 default value 0x06 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev3 rev2 rev1 rev0 dev3 dev2 dev1 dev0 0 0 0 0 0 1 1 0 device id and revision id register definition bit register name r/w definition bit 0 ~ bit 3 dev0 ~ dev2 device id bit r device id bi t to indicate device id. bit 4 ~ bit 7 rev0 ~ rev3 revision id bit r revision id bit to indicate re vision id. revision id is updated when a possible software modification is made. it is 0x00. reserved register (r) [address 0x04] sub address 0x03 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved reserved 0 0 0 0 0 0 0 0 device id and revision id register definition bit register name r/w definition bit 0 ~ bit 7 reserved reserved bit r/w reserved input control register (r/w) [address 0x05] this is an out-of-standard quality input signal control register. sub address 0x05 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 flt cbcr vd2 vd1 vd0 hd2 hd1 hd0 0 0 0 0 0 0 0 0 adjustment of sync input timing is made bit register name r/w definition bit 0 ~ bit 2 hd0 ~ hd2 hsync input delay r/w hsync signal input is delayed by the set value. hd [ 2:0 ] system clock count delay ( + 0 ~ + 7 clk delay ) bit 3 ~ bit 5 vd0 ~ vd2 vsync input delay r/w vd0 ~ vd2 vsync input delay vsync signal input is delayed by the set value. vd [ 2:0 ] system clock count delay ( + 0 ~ + 7 clk delay ) bit 6 cbcr exchange cbcr r/w cb, cr ti ming data are interchanged at cbcr = 1. bit 7 flt y flat data r/w y input data is linear- interpolated ( averaging most adjacent data ).
asahi kasei [ak8815/16] ms0331-e-00 34 2004 / 08 system connection example hsync vsync d[7:0] a nalog amp + lpf 390 ? 75 ? videoout iref vref 0.1uf a vss 12k ? a vdd 0.1uf 10uf xti xto 18pf 22pf clkout clkmd clkinv sdo sdi sclk cs rstn pdn test a tpg dvss dvcc pvdd2 pvss2 pvdd1 pvss1 ak8816
asahi kasei [ak8815/16] ms0331-e-00 35 2004 / 08 package package outline dimension 57 pin fbga -package drawing 5.0 0.1 5.0 0.1 0.5 4.0 = 0.5 8 a b c d e f g 57 ? 0.05 0.89 0.1 h j 9 0.08 s seating plane s 1 package & lead frame material package molding compound: epoxy interposer material: bt resin
asahi kasei [ak8815/16] ms0331-e-00 36 2004 / 08 marking 8816 xxxxx a. package type : bga b. pin count : 57 pins ( 1 pin for index ) c. product number : 8815 d. factory control c ode : xxxxx ( 5 digits )
asahi kasei [ak8815/16] ms0331-e-00 37 2004 / 08 ? these products and their spec ifications are subject to change without notice. befo re considering any use o r application, consult the asahi kasei mi crosystems co., ltd. (akm) sales offi ce or authorized dist ributor concerning their current status. ? akm assumes no liability for infringement of any patent, inte llectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devic es or systems containing them, may r equire an export license or other official approval under the law and regulations of the country of export pertain ing to customs and tariffs, currenc y exchange, or strategic materials. ? akm products are neither in tended nor authorized for use as critical components in any safety, life support, or othe r hazard related device or system, and akm assumes no respons ibility relating to any such use, except with the express written consent of the repres entative director of akm. as used here: (a) a hazard related device or syst em is one designed or intended for lif e support or maintenance of safet y or for applications in medicine, aeros pace, unclear energy, or other fields , in which its failure to function or perform may reasonably be expected to result in lo ss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to f unction or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectivene ss of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distri butes, disposes of, or otherwise places the product with a third party to not ify that party in advanc e of the above content and conditions, and the buyer o r distributor agrees to assume any and all responsibilit y and liability for and hold akm harmless from any and all claims arising from the use of said pr oduct in the absence of such notification. important notice

▲Up To Search▲

Price & Availability of AK8816VG

	To Download AK8816VG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .